[Storage-research-list] [Call For Participation] IA^3 2021: 11th SC Workshop on Irregular Applications: Architectures & Algorithms

[Tumeo, Antonino]

IA^3 2021
11th Workshop on Irregular Applications: Architectures and Algorithms
http://hpc.pnl.gov/IA3
November 15, 2021
Hybrid Workshop
In conjunction with SC21
In co-operation by IEEE TCHPC

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Theme
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Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms.

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Program
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9:00 - 9:10	Welcome and Introduction
		Antonino Tumeo (PNNL), Marco Minutoli (PNNL), Vito Giovanni Castellana (PNNL), John Feo (PNNL)

9:10 - 10:00	Invited Talk 1 - Chair: Marco Minutoli (PNNL)
		Project 38: Innovative Architectures for High-Performance Computing Systems
		Dr. Eric Cheng (Laboratory of Physical Sciences, University of Maryland)

10:00 - 10:30	Break

10:30 - 12:30	Paper Session 1 - Chair: Serena Curzel (Politecnico di Milano)

		Mapping Irregular Computations for Molecular Docking to the SX-Aurora TSUBASA Vector Engine
		Solis Vasquez, Focht, Koch

		Greatly Accelerated Scaling of Streaming Problems with A Migrating Thread Architecture
		Page, Kogge

		Accelerating unstructured-grid CFD algorithms on NVIDIA and AMD GPUs
		Stone, Walden, Zubair, Nielson

		No More Leaky PageRank
		Sallinen, Ripeanu

12:30 - 14:00	Lunch Break

14:00 - 15:00	Panel - Moderator: Antonino Tumeo (Pacific Northwest National Laboratory)

		Panelists: Andrew Chien (University of Chicago), Oded Green (NVIDIA), 
		Giacomo Pedretti (HPE), Ana Lucia Verbanescu (University of Amsterdam)

15:00 - 15:30	Coffee Break

15:30 - 16:20	Invited Talk 2 - Chair: Vito Giovanni Castellana (PNNL)

		Implementing Performance Portable Graph Algorithms Using Task-Based Execution
		Prof. Umit Catalyurek (Georgia Institute of Technology) 

16:20 - 17.20	Paper Session 2 - Chair: Reece Neff (North Carolina State University)

		Sparse Exact Factorization Update
		Chen, Davis, Lourenco, Moreno-Centeno

		Towards Scalable Data Processing in Python with CLIPPy
		Pirkelbauer, Bromberger, Iwabuchi, Pearce

17:20 - 17:30	Closing Remarks
		Antonino Tumeo (PNNL), Marco Minutoli (PNNL), Vito Giovanni Castellana (PNNL), John Feo (PNNL)

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Organizers
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Antonino Tumeo (PNNL)
Marco Minutoli (PNNL)
John Feo (PNNL)
Vito Giovanni Castellana (PNNL)