[Disksim-users] problem cache replacement algorithm

[Navid Farhadi]

Hi Abdul Arfan
I trace this code and the problem is 
cache->map[set].lru[0] 
that has not value in the fifo, lifo and random replacement policies. These policies are not implemented correctly. 
The value of "line" variable after this statement is 0 and then the "if (line)" condition does not satisfied. This happens because the lru[0] list does't filled correctly. You can trace these methhods:
cache_add_to_lrulist

cache_remove_from_lrulist

that modify lru linked lists.

Navid Farhadi


________________________________
 From: Abdul Arfan <abdul.arfan at gmail.com>
To: disksim-users at ece.cmu.edu 
Sent: Thursday, December 13, 2012 8:36 AM
Subject: [Disksim-users] problem cache replacement algorithm
 
Dear disksim users,

Im using disksim 4 and, try to test several cache replacement algorithm,
I set the cache size to 16 and only use a very small trace file:

100 0   1   1   1
200 0   2   1   1
300 0   3   1   1
400 0   4   1   1
500 0   5   1   1
600 0   6   1   1
700 0   7   1   1
800 0   8   1   1
900 0   9   1   1
1000 0   10   1   1
1100 0   11   1   1
1200 0   12   1   1
1300 0   13   1   1
1400 0   14   1   1
1500 0   15   1   1
1600 0   16   1   1
1700 0   17   1   1
1800 0   18   1   1
1900 0   19   1   1
2000 0   20   1   1

to know what happed I add a print statement to the cache_replace function
in file disksim_cachemem.c.

However I found that only CACHE_REPLACE_SLRU works correctly
(it runs cache_replace 4 times),
other cache algorithm CACHE_REPLACE_FIFO stop after processing the line 17
(it only runs cache_replace function 1 time).

Is there anybody experiencing the same problem?

-- 
Abdul Arfan (+82 10 4449 6652)
http://arfan86.blogspot.com
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