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<div class="">[Apologies if you receive multiple copies of this CFP]<br class="">
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<div class="">IA^3 2018 </div>
<div class="">8th Workshop on Irregular Applications: Architectures and Algorithms</div>
<div class=""><a href="http://hpc.pnl.gov/IA3" class="">http://hpc.pnl.gov/IA3</a></div>
<div class="">In Conjuction with SC18</div>
<div class="">Sponsored by IEEE TCHPC</div>
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<div class="">Call for Papers</div>
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<div class="">Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures,
and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed
graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do
not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.</div>
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<div class="">Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application
areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next
few years.</div>
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<div class="">This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis,
algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:</div>
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<div class="">- Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors </div>
<div class="">- Network architectures and interconnect (including high-radix networks, optical interconnects) </div>
<div class="">- Novel memory architectures and designs (including processors-in memory) </div>
<div class="">- Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) </div>
<div class="">- Modeling, simulation and evaluation of novel architectures with irregular workloads </div>
<div class="">- Innovative algorithmic techniques </div>
<div class="">- Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)</div>
<div class="">- Impact of irregularity on machine learning approaches</div>
<div class="">- Parallelization techniques and data structures for irregular workloads</div>
<div class="">- Data structures combining regular and irregular computations (e.g., attributed graphs)</div>
<div class="">- Approaches for managing massive unstructured datasets (including streaming data) </div>
<div class="">- Languages and programming models for irregular workloads</div>
<div class="">- Library and runtime support for irregular workloads</div>
<div class="">- Compiler and analysis techniques for irregular workloads</div>
<div class="">- High performance data analytics applications, including graph databases </div>
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<div class="">Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not
mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.</div>
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<div class="">Important Dates</div>
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<div class="">Abstract Submission: August 22, 2018</div>
<div class="">Position or Regular Paper Submission: August 29, 2018</div>
<div class="">Notification: September 28, 2018</div>
<div class="">Camera-ready: October 10, 2018</div>
<div class="">Workshop: November 12, 2018</div>
<div class="">Submissions</div>
<div class="">Submission site: <a href="https://submissions.supercomputing.org/" class="">
https://submissions.supercomputing.org</a></div>
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<div class="">Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers including figures, tables and references.</div>
<div class="">Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.</div>
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<div class="">The workshop proceedings will be published through IEEE TCHPC and will be included in the IEEE Xplore digital library.</div>
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<div class="">The templates are available at: </div>
<div class=""><a href="http://www.ieee.org/conferences_events/conferences/publishing/templates.html" class="">http://www.ieee.org/conferences_events/conferences/publishing/templates.html</a>.</div>
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<div class="">Artifact Description & Evaluation</div>
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<div class="">This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the
SC reproducibility page for further details on the rationale behind AD and AE: <a href="https://sc18.supercomputing.org/submit/sc-reproducibility-initiative/" class="">
https://sc18.supercomputing.org/submit/sc-reproducibility-initiative/</a>.</div>
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<div class="">Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent
person could replicate their results. This additional page is voluntary, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. If a paper has no computational
results, the appendix only needs to mention that computational results are not part of the paper.</div>
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<div class="">Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for
the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared pubblicly (for example, through the CK - Collective Knowledge -
<a href="https://github.com/ctuning/ck" class="">https://github.com/ctuning/ck</a> format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE
process, please refer to: <a href="http://ctuning.org/ae/submission.html" class="">
http://ctuning.org/ae/submission.html</a>. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. </div>
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<div class="">For any additional question on the AD and the AE please contact the Artifact Evaluation Chair Flavio Vella at
<a href="mailto:flavio@dividiti.com" class="">flavio@dividiti.com</a>.</div>
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<div class="">Organizers</div>
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<div class="">Antonino Tumeo (PNNL), <a href="mailto:antonino.tumeo@pnnl.gov" class="">
antonino.tumeo@pnnl.gov</a></div>
<div class="">John Feo (PNNL/NIAC), <a href="mailto:john.feo@pnnl.gov" class="">john.feo@pnnl.gov</a></div>
<div class="">Vito Giovanni Castellana (PNNL), <a href="mailto:vitoGiovanni.castellana@pnnl.gov" class="">
vitoGiovanni.castellana@pnnl.gov</a></div>
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<div class="">Proceedings Chair</div>
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<div class="">Marco Minutoli (PNNL and WSU), <a href="mailto:marco.minutoli@pnnl.gov" class="">
marco.minutoli@pnnl.gov</a></div>
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<div class="">Artifact Evaluation Chair</div>
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<div class="">Favio Vella (DIVIDITI), <a href="mailto:flavio@dividiti.com" class="">
flavio@dividiti.com</a></div>
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<div class="">Technical Program Committee</div>
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<div class="">Nesreen Ahmed, Intel, US</div>
<div class="">Kubilay Atasu, IBM Zurich, CH</div>
<div class="">Scott Beamer, LBNL, US</div>
<div class="">Sanjukta Bhowmick, University of Nebraska Omaha, US</div>
<div class="">Erik Boman, SNL, US </div>
<div class="">David Brooks, Harvard University, US</div>
<div class="">Aydin Buluc, LBNL, US </div>
<div class="">Joe Eaton, NVIDIA, US </div>
<div class="">Rajiv Gupta, UC Riverside, US </div>
<div class="">Arif Khan, PNNL, US </div>
<div class="">Farzad Khorasani, Georgia Tech, US</div>
<div class="">Peter M. Kogge, University of Notre Dame, US </div>
<div class="">Manoj Kumar, IBM TJ Watson, US</div>
<div class="">John Leidel, Tactical Computing Labs, US </div>
<div class="">Kamesh Madduri, Pennsylvania State University, US </div>
<div class="">Naoya Maruyama, LLNL, US </div>
<div class="">Miquel Moretó, Barçelona Supercomputing Center, ES </div>
<div class="">Maxim Naumov, Facebook, US </div>
<div class="">Fanny Nina-Paravecino, Northeastern University, US</div>
<div class="">Sreepathi Pai, Rochester University, US </div>
<div class="">Roger Pearce, LLNL, US</div>
<div class="">Miquel Pericas, Chalmers University of Technology, SE </div>
<div class="">Keshav Pingali, University of Texas at Austin, US</div>
<div class="">Viktor K. Prasanna, University of Southern California, US </div>
<div class="">Jason Riedy, Georgia Tech, US </div>
<div class="">John Shalf, LBNL, US</div>
<div class="">Shaden Smith, Intel, US </div>
<div class="">Edgar Solomonik, University of Illinois at Urbana-Champaign, US</div>
<div class="">Bora Uçar, French National Center for Scientific Research, FR</div>
<div class="">Ruud van der Pas, Oracle, NL</div>
<div class="">Ana Lucia Varbanescu, University of Amsterdam, NL</div>
<div class="">Cheng Wang, Microsoft, US</div>
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